电子工程专辑

RISC-V的下一个前沿：人工智能

RISC-V北美峰会上展示了采用新型矢量处理器、高速接口和外围子系统的最新CPU核心，并同步推出了配套的参考板、软件设计套件(SDK)和工具链。此次峰会还提前呈现了日益成熟的RISC-V设计生态系统。 RISC-V北美峰会在加利福尼亚州圣克拉拉举行，其间展示了采用 ...
Semiconductor Engineering

Coding And Debugging RISC-V

As monolithic device scaling continues to wind down and evolve toward increasingly heterogeneous designs, it has created an inflection point for chip architects to create customized cores that are ...
新浪网

RISC-V 2026：当三足鼎立成为事实，新的问题即将浮现

2026伊始，一条关于RISC-V市场渗透率的报道，将这个开放架构正式提升到和Arm以及x86并列的处理器架构商业地位。RISC-V 国际 ...
Electronic Design

Techniques to Minimize Code Footprint in RISC-V-Based Apps

RISC-V supported standard extensions. Hints to help the compiler make better decisions. Reasons why to avoid writing "clever code." 1. These are the standard ...
Electronic Design

Highlights from the RISC-V Summit 2024

The state of RISC-V, including new RISC-V announcements. A look at some good video presentations at the 2024 RISC-V Summit. RISC-V trends in 2025. I didn't make it to the RISC-V Summit this year.
Ars Technica

Google wants RISC-V to be a “tier-1” Android architecture

Over the holiday break, the footage from the recent “RISC-V Summit” was posted for the world to see, and would you believe that Google showed up to profess its love for the up-and-coming CPU ...